The invention relates to the field of RF wireless applications, and in particular to a novel 2V SPDT design for high power RF and microwave applications.
In a GSM wireless communication system, a basic transmit/receive (T/R) switch is required to have high linearity to prevent adding noise in the form of harmonic distortion. This is particularly difficult when transmitting at full power with low battery voltage.
For a traditional GaAs switch, the maximum linear input power Plin,max is limited by the DC control voltage Vctrl, the number of gates n, and pinch-off voltage Vp of the switch FET, which is defined as
                              P          lin_max                =                                            1                              2                ⁢                                  Z                  0                                                      ⁡                          [                              2                ⁢                                  n                  ⁡                                      (                                                                  V                        p                                            -                                              V                        ctrl                                                              )                                                              ]                                2                                    Eq        .                                  ⁢        1            The equation 1 provides a first order estimate of the maximum linear input power of a typical SPDT switch designed with a multiple gate GaAs FET.
FIGS. 1A and 1B are a circuit diagram of a traditional SPDT and a graph of the gate-to-drain voltage and gate-to-source voltage of the FETs used in the traditional SPDT, respectively. FIG. 1A is a schematic of a traditional SPDT dual-gate switch 3. The SPDT dual gate switch 3 includes FETs 1 and 2. FETs 1 and 2 include a gate (g), drain (d), and source (s). Also, the SPDT dual-gate switch 3 includes a receive port Rx, transmitter port Tx, and two DC control voltages Vctrl. The transmitter port Tx is connected to the drain of FET 1. The source of FET 1 is connected to the antenna port. Two resistors with values of R are connected in parallel, where one end of the parallel resistors is connected to the gate of FET 1 and the other end is connected to one of the two DC control voltages.
The drain of FET 2 is connected to the antenna port Ant, and the source is connected to the receiver port Rx. A second set of parallel resistors R is connected to the drain of FET 2. The other end of the second set of parallel resistors is connected to the second DC voltage control source Vctrl.
If the required Plin,max is 35 dBm, n=3, Vp=−0.3 V, and Z0=50 ohms, the highest Vctrl is 3.3 V. This means that the traditional GaAs FET T/R switch cannot handle an input power of 35 dBm without compression at the receive section of the SPDT switch, as shown in FIG. 1A.
FIG. 1B is a graph demonstrating that in the first half signal period the gate-to-drain voltage (Vgd) of the FET 1 and the gate-to-drain voltage of the FET 2 is greater than the pinch-off Vp, and in the second half signal period the gate to source voltages (Vgs) of the FETs 1 and 2 are also greater than the pinch-off voltage Vp. The problem is that whenever the Vgd or Vgs is greater than the pinch-off voltage Vp for the FETs in the off branch, the FET switch may be conducting a RF signal to ground (RF bleeding). This causes high insertion losses and power compression, which leads to the creation of harmonic distortions.
To improve the linearity at low control voltages and high power conditions, a multiple dual gate transistor structure is needed in the final design to obtain high isolation and low insertion loss at GSM and DCS frequencies.